The scaling of channel length of Metal Oxide Semiconductor Field Effect Transistors (MOSFETs) causes a number of effects that are negligible in long-channel models to become significant or even a dominant factor in performance degradation. These are known as short-channel effects. Short-channel effects may result in deteriorated electrical performance of devices, e.g., gate threshold voltage dropping, power consumption increasing, and signal-to-noise ratio (SNR) decreasing.
To control short channel effects, more impurities such as phosphorus and boron are introduced into the channel, which, however, may lead to a decreased mobility of carriers in the channel of the device, an uncontrollable abruptness of impurity distribution, or even more severe short-channel effects. Moreover, it is difficult for the conventional strained SiGe PMOS technology to provide an ever greater stress in the channel. Furthermore, the thickness of gate oxide dielectric is becoming a bottleneck since the speed at which the thickness is reduced can no longer keep up with gate width decreasing, and gate leakage currents is increasing. In addition, as the feature size shrinks, the resistance of the source/drain region is increasing and so is the power consumption of the device.
At present, a prominent solution in the art is to change the conventional planar structure, intending to reduce the thickness of the channel region and eliminate the electrical neutral layer under the depletion layer in the channel, so that the depletion layer can fill up the channel region. This is known as a Fully Depleted (FD) device, and conventional planar devices are Partially Depleted (PD) devices.
However, the manufacturing of FD devices requires an extremely thin silicon layer in the channel. Conventional manufacturing processes, especially those that are bulk silicon-based, cannot meet this requirement or are too expensive. Even for the newly developed silicon-on-insulator (SOI) technology, still, it is hard to control the thickness of the silicon layer at a desired level. Therefore, the searching for the general solution for FD devices has been directed to 3-dimensional device structures, i.e., FD double gate technique or tri-gate technique.
The 3-dimensional device structure (vertical device structure as referred to in some documents) is a technology whereby the cross-sections of the source/drain region and the gate are not in the same plane, substantially a fin field-effect transistor (FinFET) structure.
In the 3-dimensional device structure, instead of being within the bulk silicon or the SOI, the channel region is separated from these structures. Consequently, it is possible to make an FD channel having an extremely thin thickness with, e.g., etching.
A known 3-dimensional semiconductor device is shown in FIG. 1. The semiconductor device includes: a semiconductor base 20, which is on an insulation layer 10; source/drain regions 30 abutting the opposite first sides 22 of the semiconductor base 20; and gates 40, which are on the opposite second sides 24 adjacent to the first sides 22 (A gate dielectric layer and a work-function metal layer that are sandwiched between the gate 40 and the semiconductor base 20 are not shown). In order to reduce the resistance of the source/drain regions, edges of the source/drain regions 30 may be extended. As a result, the width (in xx′ direction) of the source/drain regions 30 is larger than that of the semiconductor base 20. With the width (d) of the source/drain regions 30 increased, the parasitic capacitances between the source/drain regions 30 and the gate 40, and between the source/drain regions 30 and the semiconductor base 20 increase, which may lead to an increased resistance-capacitance delay or deteriorated AC performance of the device.